A-109sとは 意味・読み方・使い方

The DLC layers 108d, 109d are formed on the inner surface of the back lid 108 and on the surface of a male screw 109s of the screw component 109.例文帳に追加

裏蓋１０８の内面、及び、ネジ部品１０９の雄ネジ１０９ｓの表面には、ＤＬＣ層１０８ｄ，１０９ｄが形成される。 - 特許庁

An input signal 100s is processed by a generating polynomial dividing circuit 101, a decoding parity check converting circuit 103, an adding circuit 104, and a majority decision logic deciding circuit 105 and further the outputs from the adding circuit 104 and majority decision logic deciding circuit 105 and an input mode signal 113s are processed by an error correction completion signal generating circuit 109 to generate an error correction completion signal 109s.例文帳に追加

入力信号１００ｓを生成多項式除算回路１０１、復号パリティチェック変換回路１０３、加算回路１０４、多数決論理判定回路１０５で処理し、更に加算回路と多数決論理判定回路からの出力と入力モード信号１１３ｓとを誤り訂正完了信号発生回路１０９で処理して誤り訂正完了信号１０９ｓを生成する。 - 特許庁