「supply voltage rejection ratio」に関連した英語例文の一覧と使い方 - Weblio英語例文検索

To provide a reference voltage circuit that operates with lower current consumption while maintaining an operation at low voltage without deteriorating a rejection ratio of power supply voltage fluctuation.例文帳に追加

電源電圧変動除去比を悪化させることなく、低電圧動作を維持したまま消費電流の低い基準電圧回路を実現すること。 - 特許庁

Therefore, even when the minimum operation voltage of the reference voltage circuit is low, the power supply rejection ratio PSRR_LF can be increased.例文帳に追加

よって、基準電圧回路の最低動作電圧が低くても、電源電圧変動除去比ＰＳＲＲ_LFは大きくなることができる。 - 特許庁

To provide a voltage regulator circuit which satisfies all of an operation voltage range, an input stability, a power supply rejection ratio, and an output temperature coefficient.例文帳に追加

動作電圧範囲、入力安定度、ＰＳＲＲ、出力温度係数すべてが満足される電圧レギュレータ回路を提供する。 - 特許庁

To provide a bandgap circuit which can be operated with a low supply voltage and has a high power supply rejection ratio (PSRR), low noise, and less variance.例文帳に追加

低電源電圧で動作可能な、高ＰＳＲＲ、低ノイズ、低ばらつきのバンドギャップ回路を提供すること。 - 特許庁

To provide a reference voltage circuit for achieving reduction in size by microfabrication process and obtaining a high power supply rejection ratio.例文帳に追加

微細プロセスによる小型化を実現しながら、高い電源電圧変動除去特性を得る基準電圧回路を提供する。 - 特許庁

To provide a circuit for eliminating fluctuation in power supply voltage capable of obtaining a stable reference voltage without being affected by fluctuations in a power supply voltage having an excellent PSRR (Power Supply Rejection Ratio) characteristic by an easier method.例文帳に追加

電源電圧の変動の影響を受けずに安定した基準電圧を得ることのできるＰＳＲＲ特性に優れた電源電圧変動除去回路を、より容易な方法で実現する。 - 特許庁

To suppress the fluctuation of an output operation point to a common mode input voltage fluctuation and to increase a power supply voltage rejection ratio as well, in a differential amplifying circuit having two sets of push-pull type CMOS inverting amplifiers.例文帳に追加

２組のプシュプル型CMOS反転増幅器を有する差動増幅回路において、同相入力電圧変動に対する出力動作点の変動を抑制するとともに、電源電圧除去比も高くする。 - 特許庁

As compared with conventional cases where an output node 14a of the VR2 generating circuit 14 is connected to the reference voltage node 13a of the D/A converter 13, without the use of the external pin P4, and the supply voltage rejection ratio becomes small.例文帳に追加

したがって、外部ピンＰ４を使用せず、ＶＲ２発生回路１４の出力のノード１４ａをＤ／Ａ変換器１３の参照電圧ノード１３ａに接続していた従来に比べ、電源電圧除去比が小さくなる。 - 特許庁

To provide a differential amplifier circuit capable of reducing consumption current in a circuit and reducing the circuit size while improving a power supply voltage rejection ratio.例文帳に追加

電源電圧変動除去比を向上させつつ、回路内の消費電流の低減及び回路自体の小型化を図ることができる差動増幅回路を提供する。 - 特許庁

Even when the power supply voltage of a power supply terminal 10 becomes low, an NMOS71 operates in a non-saturation state, and an output resistance ro71 of the NMOS71 becomes low, the power supply rejection ratio PSRR_LF is increased as an amplification degree Ao for a differential amplifier circuit 60 is increased.例文帳に追加

電源端子１０の電源電圧が低くなり、ＮＭＯＳ７１が非飽和動作し、ＮＭＯＳ７１の出力抵抗ｒｏ７１が低くなっても、差動増幅回路６０の増幅度Ａｏが大きければ、電源電圧変動除去比ＰＳＲＲ_LFも大きくなる。 - 特許庁