To provide an inverse element computing device in which circuit scale and circuit delay are suppressed further when the inverse element computing algorithm in a Galois field of a characteristic two is made into VLSI. 標数2のガロア体での逆元計算アルゴリズムをVLSI化した際、回路規模や回路遅延をより小さく抑えられる逆元計算装置を提供すること。 - 特許庁