The method for wiring the semiconductor integrated circuit adopting an array structure of a general purpose logic array as a base comprises the steps of forming wirings capable of being commonly used without depending upon designing of a user circuit by a lower layer interconnection, commonly using and staticizing the commonly usable wirings by a plurality of designing, and further customizing the more significant interconnection of the lower layer interconnection. 汎用ロジックセルのアレイ構造をベースとする半導体集積回路の配線方法において、ユーザ回路のデザインに依存せず共通化可能な配線を下層配線層で形成し、共通化可能な配線を複数のデザインで共通、且つ、固定化し、更に、下層配線層の上位の配線層をカスタマイズする。 - 特許庁