例文 | 共起表現 |
「CPUs」の共起表現一覧(1語右で並び替え)
該当件数 : 46件
JamVM currently supports the | CPUs: AMD64, ARM, i80486, MIPS, and PowerPC. |
It supports a variety of | CPUs and operating systems. |
the economics of the manufacturing processes of | CPUs and other components. |
distributed across multiple operating systems, | CPUs, and interconnects to communicate, as if they w |
he compiler itself can run on several different | CPUs) and self-hosting. |
mentations are available for a variety of other | CPUs and operating systems. |
) has been claimed to be rated at 3110 Elo on 4 | CPUs, and Rybka 3 is supposedly about 100 Elo strong |
dard thermal pastes (allowing hot chips such as | CPUs and GPUs to run several degrees cooler), but ne |
AMD | CPUs are unlocked in early editions of a model and l |
ntel 80386EX and the WDC 65C02S are static core | CPUs, as is the Freescale 683XX family. |
While slower than x86 | CPUs being sold by AMD and Intel, both in absolute t |
mplementing the instruction set for the line of | CPUs designed to run the OpenVMS operating system cr |
ut powerful command set, and, like all Motorola | CPUs, did not use memory segmentation. |
They are used for testing | CPUs, for example, when overclocking. |
iconductor announces that it will produce 65 nm | CPUs for the Xbox 360, which will lower the console' |
first top-tier computer manufacturer to utilize | CPUs from AMD and Cyrix. |
Many newer | CPUs have mechanisms to make this harder, such as a |
4 total blades containing 7168 GPUs, and 14,336 | CPUs, managed by the SLURM job scheduler. |
limited by the data source and/or the number of | CPUs near that data. |
rity with Intel's SL line and IBM's SLC line of | CPUs, neither of which was related to Cyrix's SLC. |
y code to run on host and target (or simulated) | CPUs of the same architecture. |
Intel usually has one or two Extreme Edition | CPUs on the market, leading their range in clock spe |
ow with the advances of technologies, multicore | CPUs, open source foundries, virtual machine technol |
Generation 1 68000 | CPUs primarily competed against the 16-bit 8086/8088 |
Because the Pentium 4 and other NetBurst | CPUs proved less energy efficient than the Pentium M |
One reason is that modern | CPUs strive to execute instructions in parallel via |
Some | CPUs, such as Athlon 64 and Opteron, handle main mem |
ted to be executed on a variety of machines and | CPUs that may share the same instruction set, but ha |
Analogous to the Pentium D branded | CPUs, the Kentsfields comprise two separate silicon |
in making applications optimized for multicore | CPUs, the majority of computer applications do not e |
s calculations much faster than general purpose | CPUs; they also licensed out the PhysX SDK (formerly |
Users unlock | CPUs to allow underclocking, overclocking, and front |
It is possible for | CPUs to support this, but this functionality is rare |
lesser share of the bandwidth from each of the | CPUs to the northbridge than if the dies were each t |
Some | CPUs track the load-linked address at a cache-line o |
Library, supporting the AMD Athlon and Opteron | CPUs under Linux and Windows. |
of FPGAs the ZeBu board has, and the number of | CPUs used for compilation. |
e called __float128 for x86, x86-64 and Itanium | CPUs, using a software emulation from libc6. |
th other devices in the system (including other | CPUs) using one or more slightly higher-level HyperT |
Little-endian | CPUs usually employ "LSB 0" bit numbering, however b |
In an SPMD system, both | CPUs will execute the code. |
Like their dual core Extreme predecessors, | CPUs with the Kentsfield XE core had unlocked multip |
AMD ships unlocked | CPUs with their Opteron, FX and Black Series line-up |
d tested to run in a network with at least 2000 | CPUs, with up to 10 Mio webpages per single CPU, all |
re restrictions such as lower memory, low power | CPUs with limited or no storage capabilities, small |
ocacy (SAHAYOG) sets up Child Protection Units ( | CPUs), works towards safe migration and networks wit |
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