英和和英

出典:『Wikipedia』 (2011/05/03 18:54 UTC 版)

英語による解説

引用

Dynamic timing verification refers to verifying that an ASIC design is fast enough to run without errors at targeted clock rate. This is accomplished by simulating the design files used to synthesize the Integrated Circuit design. This is in contrast to static timing analysis which has a similar goal as dynamic timing verification except does not require simulating the real functionality of the IC.